The present specification relates generally to integrated circuits and methods of manufacturing integrated circuits. More particularly, the present specification relates to enhancing gate patterning properties with reflective hard mask.
Semiconductor devices or integrated circuits (ICs) can include millions of devices, such as, transistors. Ultra-large scale integrated (ULSI) circuits can include complementary metal oxide semiconductor (CMOS) field effect transistors (FET). Despite the ability of conventional systems and processes to fabricate millions of IC devices on an IC, there is still a need to decrease the size of IC device features, and, thus, increase the number of devices on an IC.
One limitation to achieving smaller sizes of IC device features is the capability of conventional lithography. Lithography is the process by which a pattern or image is transferred from one medium to another. Conventional IC lithography uses ultra-violet (UV) sensitive photoresist. Ultra-violet light is projected to the photoresist through a reticle or mask to create device patterns on an IC. Conventional IC lithographic processes are limited in their ability to print small features, such as contacts, trenches, polysilicon lines or gate structures.
Generally, conventional lithographic processes (e.g., projection lithography and EUV lithography) do not have sufficient resolution and accuracy to consistently fabricate small features of minimum size. Resolution can be adversely impacted by a number of phenomena including: diffraction of light, lens aberrations, mechanical stability, contamination, optical properties of resist material, resist contrast, resist swelling, thermal flow of resist, etc. As such, the critical dimensions of contacts, trenches, gates, and, thus, IC devices, are limited in how small they can be.
Another difficulty arising from the continuing small dimensions involved in the creation of gate structures is the tendency in the lithography process to experience resist erosion and pattern collapse during trim etch processes. During trim etch processes, a significant amount of the resist is normally etched away in a vertical direction, resulting in a substantial weakening and thinning of the photoresist. This significant reduction of the vertical dimension or thickness of the photoresist from its untrimmed vertical dimension can promote discontinuity thereof, resulting in the photoresist being incapable of providing effective masking in the fabrication of the gate. The resist thickness erosion occurs during etch processes. Exemplary trim processes are described in U.S. Pat. No. 5,965,461 entitled CONTROLLED LINEWIDTH REDUCTION DURING GATE PATTERN FORMATION USING A SPIN-ON BARC.
Thus, there is a need to optimize gate patterning and generate a hard mask to control gate final sizes. Further, there is a need for a method of enhancing gate patterning properties with reflective hard mask. Yet further, there is a need to use imaging layers to define gate structures having small critical dimensions.
An exemplary embodiment is related to a method of fabricating an integrated circuit. This method can include depositing a reflective metal material layer over a layer of a polysilicon, depositing an anti-reflective coating over the reflective metal material layer, trim etching the anti-reflective coating to form a pattern, etching the reflective metal material layer according to the pattern, and removing portions of the polysilicon layer using the pattern formed from the removed portions of anti-reflective coating.
Another exemplary embodiment is related to a method of optimizing optical properties of gate patterning to control gate size in an integrated circuit fabrication process. The method can include providing a reflective metal layer over a gate material layer, providing a mask layer over the reflective metal layer, and patterning the gate material layer including selectively etching the mask layer and the reflective metal layer.
Another exemplary embodiment is related to a method of forming a gate in an integrated circuit. This method can include providing a gate material layer, providing a reflective metal layer over the gate material layer, providing an anti-reflective coating (ARC) layer over the reflective metal layer, providing a resist layer over the ARC layer, and patterning a gate structure in the gate material layer by selectively removing portions of the resist layer, ARC layer, and gate material layer.
Other principle features and advantages of the invention will become apparent to those skilled in the art upon review of the following drawings, the detailed description, and the appended claims.